The present invention relates to a buffer storage device based on storage management techniques and, more particularly, to a buffer storage device adapted to provide a cache memory in an information processing system typically operating on the buffer storage principle.
Some prior art microcomputers operating on the buffer storage principle have used a cache memory accommodating frequently used data items taken from the main memory (composed of dynamic RAM, etc.). A storage management unit known as a cache controller is used to control cache memory operations so as to improve the throughput of such microcomputers.
The cache memory is accessed by a microprocessor unit (MPU) using its output of a logical address. When desired data is found in the cache memory, which is an operation called a hit, the MPU immediately obtains the data therefrom. Thus the arrangement helps improve the system throughput.
The cache controller takes the address output from the MPU and compares it with another, internally held address called a tag. If it is judged upon comparison that the required data is not found in the cache memory, a "miss" signal is output. In response, the MPU gains access to the main memory to obtain the data ("Nikkei Electronics," pp. 170-171; Nov. 16, 1987 issue; Nikkei-McGraw-Hill, Inc.)
A majority of memory systems operating on an error-correcting principle called the ECC (error-correcting code) method usually generate an ECC for each one-word data item (4 bytes long). This is now generally the case as 32-bit MPU's have gained widespread acceptance. As a result of this, data is most often transferred between cache memory and main memory in words.
There are two kinds of cache memory system: a write-through system and a copy-back system. The write-through system involves, when the MPU writes data to the cache memory, having the main memory correspondingly updated immediately after a data array write operation. With the copy-back system, the main memory is updated upon block replacement.
In addition, prior art cache memories have not been equipped with the so-called partial-write function. This is a function that updates only one byte of data inside the cache memory as desired.